Back in 2010, Massachusetts Institute of Technology (MIT) researchers explored the creation of tiny circuits using molecules to arrange themselves into useful patterns and published a paper detailing the subject in Nature Nanotechnology that same year.
The issue then was that manufacturing chips have gotten to the point that miniaturization and etching the chip using light has become smaller than the wavelength of light used to make them. Ultimately, they were able to solve the problem using electron-beam lithography and specially designed polymers that arrange themselves in useful patterns.
Researchers at the MIT and the University of Chicago came up with unique solutions involving self-assembly that could advertently be used to cram various features onto small chip geometries. According to Computerworld, the technology is a way to continue Moore's Law that has helped shrink and make computing devices cheaper for the last 50 years.
The research is a step up of that done back in 2010; it also adds a step in today's existing chip manufacturing technologies. The study is focused on the self-assembly of wires on chips. Instead of employing existing methods of etching fine features onto silicon, block copolymers are used that would expand and self-assemble into predefined designs and structures.
Current chips are being manufactured using the 10nm process, and it has become more difficult to fit minute transistors using the same wavelength. Even with the use of a new process, Extreme ultra-violet (EUV) lithography, it has presented its own set of challenges to deploying.
MIT claims the new technology can be applied to existing manufacturing technologies without complications. With standard lithography, a block copolymer, that has two different polymers connected like a chain, are placed on the predetermined surface pattern to create wires.
Once that is done, another protective polymer is placed on the block polymer employing what is called a chemical vapor deposition. This makes the block copolymers to arrange itself into vertical layers, similar to how 3D transistors are made today.
The new technology can likewise be used to create complex patterns and layers that self-assemble, and shrink the chip manufacturing process even further down to 7nm. A paper on the technology is published recently in Nature Nanotechnology journal.
